For standing out in the highly competitive market, better function and lower cost are two key factors for integrated circuit (IC) products. However, better function generally means more complex circuit and larger die area, and thereby higher cost. As shown in FIG. 1, a flyback converter 100 uses a PWM controller 180 to operate it in constant frequency current mode and processing the line voltage VIN into an isolated direct current (DC) output voltage VOUT. The PWM controller 180 provides a PWM signal SD for a power stage 110, and a feedback circuit 150 generates a feedback signal Sfb for the PWM controller 180 according to the output voltage VOUT in order to regulate the output voltage VOUT within an adjustable range. In the power stage 110, the input voltage VIN is coupled to a primary coil 116 of a transformer 114, power is delivered to a secondary coil 118 of the transformer 114 by using the PWM signal SD to switch a switch 120 coupled between the primary coil 116 and a ground terminal GND, to charge a capacitor 126 to generate the output voltage VOUT, and a resistor 122 is coupled between the switch 120 and the ground terminal GND to generate a current sense signal Scs that is fed back to a current sense pin CS of the PWM controller 180. The PWM controller 180 modulates the duty cycle of the switch 120 with the PWM signal SD, and accordingly regulates the output voltage VOUT. FIG. 2 depicts a portion of the circuit inside the PWM controller 180, in which a feedback compensation signal Scomp is generated from the feedback signal Sfb provided by the feedback pin FB, a leading edge blanking (LEB) signal SLEB is generated from the current sense signal Scs provided by the current sense pin CS, an oscillator 210 provides a clock 212, a maximum duty limit DMAXB and a current limiting signal 218, a comparator 220 generates a current comparator output CCO by comparing the feedback compensation signal Scomp and LEB signal SLEB, a comparator 222 generates a current limiting output CLO by comparing the LEB signal SLEB and current limiting signal 218, an OR gate 224 generates a reset signal R for a latch 226 according to the signals CCO and CLO, the set input S of the latch 226 receives the clock 212, and an AND gate 228 determines the PWM signal SD according to the maximum duty limit DMAXB and the output Q of the latch 226.
Referring back to FIG. 1, for the purpose of meeting electromagnetic interference (EMI) requirements, an EMI filter will be needed in the front of the input VIN to filter out EMI noise, thereby increasing the size and cost of the flyback converter 100. The size of an EMI filter increases with the increasing of the EMI noise to be filtered out. Frequency jittering is the trend in the latest AC/DC converter because it saves the cost in EMI filtering. Generally, the jitter function is implemented by logic circuit with counter. For example, U.S. Pat. No. 6,249,876 to Balakrishnan, et al. describes a digital frequency jittering circuit using a counter to generate a low-frequency envelope. To modulate a switching frequency, such as 67 KHz or 134 KHz in a low-frequency envelop, such as 4 ms period, a big counter is needed. As is well known, counter is made of T flip-flop which is a very die area consuming component. Typically, a T flip-flop costs the same area as a 5 pF capacitor, and a big counter consumes relatively large die area accordingly. Analog frequency jittering circuit generates a low frequency envelop by charging a large capacitor with a small current and therefore, it also consumes a relatively large die area. Though frequency jittering facilitates reducing the size of EMI filter, it disadvantageously bulks the size of a PWM controller.
On the other hand, some more circuits may be equipped to a PWM controller for various functions. For example, a deglitch circuit may be provided for preventing a flyback converter from malfunction caused by noise, and a soft-start circuit may be for protecting a flyback converter from being damaged by over current during power-on. These circuits significantly increase the die area and cost of a PWM controller. U.S. Pat. Nos. 6,107,851 and 6,229,366 to Balakrishnan, et al. integrate the soft-start and frequency jittering of a PWM controller into a circuit for the purpose of reducing the die area and cost of the PWM controller. However, a PWM controller may include some other functions which take long time for event verification, for example the detections of overload, light load, feedback open, optocoupler short or brownout. It is very area consuming to generate a long time constant in an IC. Consequently, reducing the die area of a PWM controller is limited.
As a remedy, a PWM controller having a shared frequency jittering circuit uses a low-frequency envelop generated by the frequency jittering circuit to provide a long time for the circuit that requires long time for operation or verification, to save the die area for RC circuit. As shown in FIG. 3, in a PWM controller 300 using a digital frequency jittering circuit, for a feedback open detector 310, an overload detector 312, a brownout detector 314, an optocoupler short detector 316 and an oscillator 322 to share a main counter 324, a clock diverting circuit 320 selects one from the outputs of the above circuits as the input clock of the main counter 324. In normal operation, the main counter 324 counts the clock provided by the oscillator 322 to trigger a frequency jittering 328 and a soft-start timer 330. When any one of the feedback open detector 310, overload detector 312, brownout detector 314 and optocoupler short detector 316 detects a fault, the detection signal generated therefrom possesses the highest priority to be the input of the main counter 324. Thus, the main counter 324 takes the detection signal as the clock for counting, and a sub counter 326 acts as a downstream of the main counter 324 for increasing the counting time so as to substitute an RC circuit that conventionally provides delay time. A judgment and diverting circuit 332 identifies whether the detected fault is true in accordance with the counting result of the sub counter 326. If yes, a proper protection function 334, such as power-off, is conducted; otherwise, the normal operation 336 is recovered. The counting time generated by the sub counter 326 is longer than the required RC delay time so as to enhance the reliability of the verification. However, this PWM controller 300 still requires the detectors 310-316 to conduct detection functions. Also, for precisely distributing the proper clock to the main counter 324, the clock diverting 320 is typically implemented by extremely complex circuit. Therefore, less die area reduction can be achieved. As shown in FIG. 4, even if the oscillator 322 and frequency jittering 328 are grouped together, for example as a normal operation circuit, and the feedback open detector 310, overload detector 312, brownout detector 314 and optocoupler short detector 316 are grouped together, for example as a fault detection circuit 338, to simplify the clock diverting circuit 320, it may frequently happen that the transient or noise during normal operation detonates the fault detection circuit 338 and renders the main counter 324 to bypass the normal operation circuit and to disturb the frequency jittering 328, which consequently causes significant inconvenience of the use of the PWM controller 300.